Automation of INTEX SWG

Apr 20, 2021
14
Spain
Pool Size
10700
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
Hi all,

As I have no much time, I'm gonna share what I have (is working now in my SWG). Remember that is a Work In Progress code, so any contribution or idea will be very much appreciated.

For this project, original cable between display board and main board will now be from display board to ESP32 board. You'll need a new cable to connect ESP32 board to the main board. This way the ESP32 will be in the middle of every comunication. For the new cable I used a NEMA17 motor cable (the one that 3D printers use) as I had several ones at home, and one connector fits what I need, so only have to change the other connector from this cable.

Here is the repo:

For the circuit you'll need:
- ESP32
- Relay module
- Power supply, I used 5V, but you can use 3.3V instead (wiring is different!)
- 2x Female and 1x Male XH2.54 4pin connectors (they are the most similar I've found that fits original cable)
- Level shifter as the logic from ESP32 is 3.3V and the SWG logic is 5V.
- Fuse for the power supply (optional)
- NEMA17 cable (I used this because I had several ones at home, but you can use whatever you have or you can buy)

For the wiring, take into account the ESP32 pins:
- GPIO 19 -> SWG main board clock
- GPIO 18 -> SWG main board data
- GPIO 17 -> Display board clock
- GPIO 16 -> Display board data
- GPIO 0 -> Relay module control

As I haven't done any schematics yet, guessing which wire is everyone on the original cable between the main board and the display board is on you. Check the schematic of the display controller (TM1650) which is in Documentation folder within the repository. The pins you need to check on the TM1650 are the following:
- PIN2 clock
- PIN3 Data
- PIN4 GND
- PIN 10 VDD (+5V)
Once you've indentified these pins, you can easily identify wich pin in the cable corresponds to every pin in the TM1650, and you'll be able to properly connect it to the level shifter, and from here to the proper pins on the ESP32.

Main power wire must be disconnected from the main board within the machine to be able to fully control power from the ESP32 (and avoid turning on itself depending on it's programming). Instead, this cable now goes to the relay module and to the input of the power supply in ESP32 board. The output of the relay goes were the original power wire was connected before on the main board. Now the ESP32 can turn ON and OFF the machine. By default when the system is powered, the ESP32 goes to standby mode, which means the machine has power and can be controlled using the default factory buttons. If the ESP32 powers OFF the machine, it won't be available to be operated using the buttons, and will only able to go back to standy state using the Rest API, or unplugging and plugging back the system. This way I've kept factory behaviour.

Before using the API, first you'll need to configure the WIFI on the ESP32. For that this project includes the wifi manager which allows you to scan and set a wifi configuration easily from your phone, as ESP32 will create its own wifi for that. If you use the console and the USB connection you'll see the assigned IP. I strongly recomend you associate the IP to the MAC address in your router configuration to make sure every time DHCP on your router assings IP to the system, the IP remains the same (I haven't implemented anything yet to specify a custom static IP from the phone).

For the API to control the system there are some endpoints that you could check in the code.
Basic API calls are the following:
- Control the machine
POST http://ip_addr:8080/api/v1/intex/swg
{
"data": {
"power": "{on|off|standby}"
}
}

- Get current status and info
GET http://ip_addr:8080/api/v1/intex/swg

- OTA Update
http://ip_addr:8080

Hope I can find the time to create a propper documentation with schematics, pictures, credits and agreements to other projects that I used. If you have any problem with this or you need help, feel free to ask, I'll try to help you.

Enjoy!
 
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Reactions: Jings

jressel01

Member
Jul 19, 2021
21
Germany
Pool Size
36000
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
hello tony,
nice to hear from you. the github link doesn't work.
in your github there is only "esp32-wifi-manager".
Regards
Jürgen
 

jressel01

Member
Jul 19, 2021
21
Germany
Pool Size
36000
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
Hi Tony,
i try to Build but i get an Error:
../main/IntexSWG.cpp:28:10: fatal error: wifi_manager.h: No such file or directory
#include "wifi_manager.h"
if i take the wifi_manager.h file from your other Projekt it dont work
[2/3] Linking CXX executable IntexSWG.elf
FAILED: IntexSWG.elf
cmd.exe /C "cd . && C:\Users\Diag\.espressif\tools\xtensa-esp32-elf\esp-2021r1-8.4.0\xtensa-esp32-elf\bin\xtensa-esp32-elf-g++.exe -mlongcalls -Wno-frame-address @CMakeFiles\IntexSWG.elf.rsp -o IntexSWG.elf && cd ."
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: esp-idf/main/libmain.a(IntexSWG.cpp.obj):(.literal._Z6RTOS_2Pv+0x1c): undefined reference to `wifi_manager_clear_wifi_configuration'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: esp-idf/main/libmain.a(IntexSWG.cpp.obj):(.literal.app_main+0x44): undefined reference to `wifi_manager_start'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: esp-idf/main/libmain.a(IntexSWG.cpp.obj):(.literal.app_main+0x48): undefined reference to `wifi_manager_fetch_wifi_sta_config'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: esp-idf/main/libmain.a(IntexSWG.cpp.obj):(.literal.app_main+0x4c): undefined reference to `wifi_manager_set_callback'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: esp-idf/main/libmain.a(IntexSWG.cpp.obj): in function `RTOS_2(void*)':
c:\intex-swg-iot-master\intex-swg-iot-master\build/../main/IntexSWG.cpp:488: undefined reference to `wifi_manager_clear_wifi_configuration'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: esp-idf/main/libmain.a(IntexSWG.cpp.obj): in function `app_main':
c:\intex-swg-iot-master\intex-swg-iot-master\build/../main/IntexSWG.cpp:687: undefined reference to `wifi_manager_start'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: c:\intex-swg-iot-master\intex-swg-iot-master\build/../main/IntexSWG.cpp:687: undefined reference to `wifi_manager_fetch_wifi_sta_config'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: c:\intex-swg-iot-master\intex-swg-iot-master\build/../main/IntexSWG.cpp:690: undefined reference to `wifi_manager_set_callback'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: c:\intex-swg-iot-master\intex-swg-iot-master\build/../main/IntexSWG.cpp:690: undefined reference to `wifi_manager_set_callback'
c:/users/diag/.espressif/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/bin/../lib/gcc/xtensa-esp32-elf/8.4.0/../../../../xtensa-esp32-elf/bin/ld.exe: c:\intex-swg-iot-master\intex-swg-iot-master\build/../main/IntexSWG.cpp:728: undefined reference to `wifi_manager_set_callback'
collect2.exe: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.
ninja failed with exit code 1
PS C:\intex-swg-iot-master\intex-swg-iot-master>
 
Last edited:

jressel01

Member
Jul 19, 2021
21
Germany
Pool Size
36000
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
i flasch the ESP first with esp32-wifi manager and it work.

i reflash the ESP with intex-swg-iot. no error but i get no wifi Access point.
Output from Monitor in Loop:
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4784
load:0x40078000,len:13700
ho 0 tail 12 room 4
load:0x40080400,len:3188
0x40080400: _init at ??:?

entry 0x40080610
I (423) cpu_start: Pro cpu up.
I (423) cpu_start: Starting app cpu, entry point is 0x40081324
0x40081324: call_start_cpu1 at C:/Users/Diag/Desktop/esp-idf/components/esp_system/port/cpu_start.c:141

I (0) cpu_start: App cpu up.
I (437) cpu_start: Pro cpu start user code
I (437) cpu_start: cpu freq: 240000000
I (437) cpu_start: Application information:
I (442) cpu_start: Project name: IntexSWG
I (447) cpu_start: App version: 1
I (451) cpu_start: Compile time: Oct 1 2021 13:51:07
I (457) cpu_start: ELF file SHA256: e7bf3f6f3d0393fb...
I (463) cpu_start: ESP-IDF: v4.3.1-dirty
I (469) heap_init: Initializing. RAM available for dynamic allocation:
I (476) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (482) heap_init: At 3FFB9490 len 00026B70 (154 KiB): DRAM
I (488) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (495) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (501) heap_init: At 40093CE4 len 0000C31C (48 KiB): IRAM
I (508) spi_flash: detected chip: generic
I (512) spi_flash: flash io: dio
ets Jun 8 2016 00:22:57
 
Last edited:

jressel01

Member
Jul 19, 2021
21
Germany
Pool Size
36000
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
I have set up a Raspi with Debian and checked out the files. Build and Flash without error or warnings. But I get just as far. I have a boot loop. It doesn't work. what am I doing wrong?
 
Apr 20, 2021
14
Spain
Pool Size
10700
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
Hi, I've been away as I have not much time lately, let me check some stuff in the repo and I'll come back to you ASAP. Boot loop could be a core panic. Core 1 is entirely dedicated to bus communication, so Watch dog must be disabled. All necessary configuracions should be in the repo, but I'll double check. If everything is ok we can check all the steps you followed to compile.

Regards,
 

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jressel01

Member
Jul 19, 2021
21
Germany
Pool Size
36000
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
i set the Loglevel to Debug.
after this the ESP reboot. No Wifi Accesspoint
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4784
load:0x40078000,len:13700
ho 0 tail 12 room 4
load:0x40080400,len:3188
0x40080400: _init at ??:?

entry 0x40080610
I (429) cpu_start: Pro cpu up.
I (429) cpu_start: Starting app cpu, entry point is 0x40081338
0x40081338: call_start_cpu1 at C:/Users/Diag/Desktop/esp-idf/components/esp_system/port/cpu_start.c:141

I (0) cpu_start: App cpu up.
D (436) clk: RTC_SLOW_CLK calibration value: 3334054
I (448) cpu_start: Pro cpu start user code
I (448) cpu_start: cpu freq: 240000000
I (448) cpu_start: Application information:
I (452) cpu_start: Project name: IntexSWG
I (457) cpu_start: App version: 1
I (462) cpu_start: Compile time: Nov 7 2021 10:16:17
I (468) cpu_start: ELF file SHA256: bcf6ae0a60cb347b...
I (474) cpu_start: ESP-IDF: v4.3.1-dirty
D (479) memory_layout: Checking 7 reserved memory ranges:
D (485) memory_layout: Reserved memory range 0x3ffae000 - 0x3ffae6e0
D (491) memory_layout: Reserved memory range 0x3ffb0000 - 0x3ffb94f0
D (498) memory_layout: Reserved memory range 0x3ffe0000 - 0x3ffe0440
D (504) memory_layout: Reserved memory range 0x3ffe3f20 - 0x3ffe4350
D (510) memory_layout: Reserved memory range 0x40070000 - 0x40078000
D (517) memory_layout: Reserved memory range 0x40078000 - 0x40080000
0x40080000: _WindowOverflow4 at C:/Users/Diag/Desktop/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

D (523) memory_layout: Reserved memory range 0x40080000 - 0x40093d48
0x40080000: _WindowOverflow4 at C:/Users/Diag/Desktop/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

D (530) memory_layout: Building list of available memory regions:
D (536) memory_layout: Available memory region 0x3ffae6e0 - 0x3ffb0000
D (543) memory_layout: Available memory region 0x3ffb94f0 - 0x3ffc0000
D (549) memory_layout: Available memory region 0x3ffc0000 - 0x3ffc2000
D (556) memory_layout: Available memory region 0x3ffc2000 - 0x3ffc4000
D (562) memory_layout: Available memory region 0x3ffc4000 - 0x3ffc6000
D (569) memory_layout: Available memory region 0x3ffc6000 - 0x3ffc8000
D (575) memory_layout: Available memory region 0x3ffc8000 - 0x3ffca000
D (582) memory_layout: Available memory region 0x3ffca000 - 0x3ffcc000
D (589) memory_layout: Available memory region 0x3ffcc000 - 0x3ffce000
D (595) memory_layout: Available memory region 0x3ffce000 - 0x3ffd0000
D (602) memory_layout: Available memory region 0x3ffd0000 - 0x3ffd2000
D (608) memory_layout: Available memory region 0x3ffd2000 - 0x3ffd4000
D (615) memory_layout: Available memory region 0x3ffd4000 - 0x3ffd6000
D (622) memory_layout: Available memory region 0x3ffd6000 - 0x3ffd8000
D (628) memory_layout: Available memory region 0x3ffd8000 - 0x3ffda000
D (635) memory_layout: Available memory region 0x3ffda000 - 0x3ffdc000
D (641) memory_layout: Available memory region 0x3ffdc000 - 0x3ffde000
D (648) memory_layout: Available memory region 0x3ffde000 - 0x3ffe0000
D (655) memory_layout: Available memory region 0x3ffe0440 - 0x3ffe3f20
D (661) memory_layout: Available memory region 0x3ffe4350 - 0x3ffe8000
D (668) memory_layout: Available memory region 0x3ffe8000 - 0x3fff0000
D (674) memory_layout: Available memory region 0x3fff0000 - 0x3fff8000
D (681) memory_layout: Available memory region 0x3fff8000 - 0x3fffc000
D (688) memory_layout: Available memory region 0x3fffc000 - 0x40000000
D (694) memory_layout: Available memory region 0x40093d48 - 0x40094000
D (701) memory_layout: Available memory region 0x40094000 - 0x40096000
D (707) memory_layout: Available memory region 0x40096000 - 0x40098000
D (714) memory_layout: Available memory region 0x40098000 - 0x4009a000
D (721) memory_layout: Available memory region 0x4009a000 - 0x4009c000
D (727) memory_layout: Available memory region 0x4009c000 - 0x4009e000
D (734) memory_layout: Available memory region 0x4009e000 - 0x400a0000
I (740) heap_init: Initializing. RAM available for dynamic allocation:
D (748) heap_init: New heap initialised at 0x3ffae6e0
I (753) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
D (759) heap_init: New heap initialised at 0x3ffb94f0
I (764) heap_init: At 3FFB94F0 len 00026B10 (154 KiB): DRAM
I (770) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (777) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
D (783) heap_init: New heap initialised at 0x40093d48
I (788) heap_init: At 40093D48 len 0000C2B8 (48 KiB): IRAM
D (795) intr_alloc: Connected src 46 to int 2 (cpu 0)
D (800) FLASH_HAL: extra_dummy: 1
D (803) spi_flash: trying chip: issi
D (807) spi_flash: trying chip: gd
D (810) spi_flash: trying chip: mxic
D (814) spi_flash: trying chip: winbond
D (818) spi_flash: trying chip: generic
I (821) spi_flash: detected chip: generic
I (826) spi_flash: flash io: dio
D (830) cpu_start: calling init function: 0x40149844
0x40149844: _GLOBAL__sub_I__ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/gcc/libstdc++-v3/src/c++11/locale-inst.cc:380

D (835) cpu_start: calling init function: 0x4014681c
0x4014681c: _GLOBAL__sub_I__ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/gcc/libstdc++-v3/src/c++11/locale-inst.cc:380

D (840) cpu_start: calling init function: 0x4013fe94
0x4013fe94: _GLOBAL__sub_I__ZN9__gnu_cxx9__freeresEv at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/gcc/libstdc++-v3/libsupc++/eh_alloc.cc:348

D (845) cpu_start: calling init function: 0x4013f8d0
0x4013f8d0: _GLOBAL__sub_I__ZNSt12ctype_bynameIwEC2ERKSsj at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/gcc/libstdc++-v3/src/c++11/locale-inst.cc:380

D (850) cpu_start: calling init function: 0x40138b94
0x40138b94: _GLOBAL__sub_I__ZNSt12ctype_bynameIcEC2ERKSsj at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/gcc/libstdc++-v3/src/c++11/locale-inst.cc:380

D (855) cpu_start: calling init function: 0x40131524
0x40131524: _GLOBAL__sub_I___cxa_get_globals_fast at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/gcc/libstdc++-v3/libsupc++/eh_globals.cc:145

D (860) cpu_start: calling init function: 0x4008854c
0x4008854c: esp_reset_reason_init at C:/Users/Diag/Desktop/esp-idf/components/esp_system/port/soc/esp32/reset_reason.c:73

D (865) cpu_start: calling init function: 0x400e2164
0x400e2164: s_set_default_wifi_log_level at C:/Users/Diag/Desktop/esp-idf/components/esp_wifi/src/wifi_init.c:72

D (870) cpu_start: calling init function: 0x400dbd64
0x400dbd64: esp_ipc_init at C:/Users/Diag/Desktop/esp-idf/components/esp_ipc/ipc.c:88

D (876) cpu_start: calling init function: 0x400d7b28
0x400d7b28: _GLOBAL__sub_I_flash_status at c:\swg\build/../main/RestServer.cpp:758

D (883) cpu_start: calling init function: 0x400d6974
0x400d6974: _GLOBAL__sub_I_module at c:\swg\build/../main/IntexSWG.cpp:738
 

Jings

Member
Aug 5, 2021
12
Norway
Hi all,

As I have no much time, I'm gonna share what I have (is working now in my SWG). Remember that is a Work In Progress code, so any contribution or idea will be very much appreciated.

<SNIP>

Hope I can find the time to create a propper documentation with schematics, pictures, credits and agreements to other projects that I used. If you have any problem with this or you need help, feel free to ask, I'll try to help you.

Enjoy!

Thanks for designing this, and for taking the time to writeup what you've got!
I guess I'll have to build this during the winter season. This is excactly what I've been looking for to get some more control of the SWG and pump.

I've managed to compile the code using the Espressif IDE, now I just need to order some ESP32 to test things out. :)

I've got the same SWG and pump as you, am I correct in assuming that the hardware you use to control the pump identical to the SWG circuit?

Based on your writings above, and the photos previously in this thread, I drew a schematic of the circuit in KiCad. (be gentle, first time I've used KiCad). Hopefully it's correct

I made a PCB as well, more or less identical to the layout you have, but I need to work on it some more , as the boardhouses dosn't like the gerbers, as they are now. is.

Did you publish the 3D-cad mounting brackets as well, somewhere? I have a vague recollection that I found something on Thingiverse, but it might be my imagination?

(I'll upload the KiCad files as well, if I manage to get something useful out of the PCB design)


EDIT: See below for correct schematic

EDIT: See below for updated boardlayout
 
Last edited:

Jings

Member
Aug 5, 2021
12
Norway
I managed to finish the PCB, and got some PCBs made. Looks ok, but I'm missing some components before I can verify that everything is correct. If there is any interest, I can clean up the files an publish the KiCad files/gerbers on github.

Regarding the code: I've managed to compile the code without errors using Visual Studio Code / ESP-IDF. But when I flash the code to the ESP32-DevkitC I've got, I end up getting the same errors as jressel01:

ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode: DIO, clock div:2
load:0x3fff0030,len:4768
load:0x40078000,len:13700
ho 0 tail 12 room 4
load:0x40080400,len:3188
entry 0x40080610
I (424) cpu_start: Pro cpu up.
I (424) cpu_start: Starting app cpu, entry point is 0x40081324
I (0) cpu_start: App cpu up.
I (438) cpu_start: Pro cpu start user code
I (438) cpu_start: cpu freq: 240000000
I (438) cpu_start: Application information:
I (442) cpu_start: Project name: IntexSWG
I (447) cpu_start: App version: 1
I (452) cpu_start: Compile time: Dec 2 2021 17:31:59
I (458) cpu_start: ELF file SHA256: 1df52a4631524354...
I (464) cpu_start: ESP-IDF: v4.3.1
I (469) heap_init: Initializing. RAM available for dynamic allocation:
I (476) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (482) heap_init: At 3FFB9470 len 00026B90 (154 KiB): DRAM
I (488) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (495) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (501) heap_init: At 40093CE4 len 0000C31C (48 KiB): IRAM
I (508) spi_flash: detected chip: generic
I (512) spi_flash: flash io: dio


Before the ESP32 reboots and boot-loops:
ets Jul 29 2019 12:21:46

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode: DIO, clock div:2
load:0x3fff0030,len:4768
load:0x40078000,len:13700
ho 0 tail 12 room 4
load:0x40080400,len:3188
entry 0x40080610



I'm missing all connections to the external circuitry, but I assume this shouldn't cause any resets?
 
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Jings

Member
Aug 5, 2021
12
Norway
Ok, I've never used Espress ESP-IDF before, or an ESP32 so this took some time debugging...

It's the watchdog timer that resets the ESP32 after 9 seconds. If I use the "idf.py menuconfig" to disable the "Use RTC watchdog in the start code" the ESP32 hangs indefinitely after spi_flash: flash io: dio but before cpu_start.
I then added a single printf in main, and stripped down everything, line by line , until I got the code booting.

The fix:/workaround to get the ESP32 to boot:
If I comment out the line "TM1650 module(dataDispPin, clockDispPin, 2, true, 3, TM1650_DISPMODE_4x8);;" and the three places this is used under "void sendDataToDisplay" (in IntexSWG.cpp) I get the ESP32 to boot, and present an access point.

I presume the rest of the code might work now, but without the possibility to send data to the display.

Will debug some more, but just wanted to share my progress so far

Actually, the missing display _might_ cause this, as this is connected to the ESP32 even if the rest of the unit is turned off. But we'll see after some more debugging
 
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jressel01

Member
Jul 19, 2021
21
Germany
Pool Size
36000
Surface
Vinyl
Chlorine
Salt Water Generator
SWG Type
Intex Krystal Clear
Hi Jings,
your schematic is not OK.
The Pins for Data an clock ok but the Label must be switched.
IO16-Data LV1-HV1 Pin 1 Intex
IO17-CLK LV2-HV2 Pin 2 Intex
IO18-Data LV3-HV3 Pin 1 Intex
IO19-CLK LV4-HV4 Pin 2 Intex
The Intex Connector have Data,CLK,5V,GND. You must switch3 and 4
 

Jings

Member
Aug 5, 2021
12
Norway
The Pins for Data an clock ok but the Label must be switched.

Thanks.
Yes, I see that I have them correctly in my notes, just swapped them when I labeled them in the schematic I guess. I'll fix it

The Intex Connector have Data,CLK,5V,GND. You must switch3 and 4

Ok, are you sure? I've based the design on the picture of the original vero board, and on this the GND pin from the ESP32 is clearly connected to "pin 3" on the connector?
(Note that the PCB is "mirrored" in this picture, aka you are viewing it from "top-side", through the board)
 

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